74HC595D / 74hc595v / 74hc595p rev 2.2 2013-11-21 8-bit shift registers with output latches general description the 74hc595 high speed shift register utilizes advanced silicon-gate cmos technology. this device possesses the high noise immunity and low power consumption of standard cmos integrated circuits, as well as the ability to drive 15 ls-ttl loads. this device contains an 8-bit serial-in, pa rallel-out shift register that feeds an 8-bit d-type storage register. the storage register has 8 3-state outputs. separate clocks are provided for both the shift register and the storage register. the shift regist er has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. both the shift register and storage register use positive-edge triggered clocks. if both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. features low quiescent current: 80a maximum low input current: 1a maximum 8-bit serial-in, parallel-out shift register with storage wide operating voltage range: 2v?6v cascadable shift register has direct clear guaranteed shift frequency: dc to 30 mhz package: sop16(74hc595 d ), tssop16(74hc595v), dip16(74hc595p) connection diagram 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 q q q q q q q q gnd vc c ser g rck sck sclr q ' a b c d e f g h h 74hc595 sop16(74hc595 d ), tssop16( 74hc595v), dip16(74hc595p) tiger electronic co.,ltd
74hc595 rev 2.2 2013-11-21 2/7 pin function pin name i/o description 15 1 7 qa qh o 8 bit 3-state output 8 16 gnd vcc grond, supply 9 q?h o serial output 10 sclr i shift register cleared 11 sck i shift register clocked 12 rck i output register clocked 13 g i output state control 14 ser i data input truth table rck sck sclr g description x x x h qa to qh = 3-state x x l l shift register cleared, q?h =0 x h l shift register clocked,q n = qn- 1 q0= ser x h l contents of shift register transferred to output latches
74hc595 rev 2.2 2013-11-21 3/7 logic diagram q d r q d q d r q d q d r q d q d r q d q d r q d q d r q d q d r q d q d r q d 1 2 3 4 5 6 7 9 10 11 12 13 14 15 q q q q q q q q q sck sclr ser rck g a b c d e f g h h ' parallel data outputs serial dat a out put
74hc595 rev 2.2 2013-11-21 4/7 timing diagram absolute maximum ratings parameter symbol scope unit supply voltage v cc -0.5 7.0 v dc input voltage v in -1.5 v cc +1.5 v dc output voltage v out -0.5 v cc +0.5 v dc output current i out 35 ma dc v cc or gnd current i cc 70 ma power dissipation p d 600 mw storage temperature range t stg -65 150 recommended operating conditions parameter symbol condition min max unit supply voltage v cc 2 6 v dc input or output voltage v in v out 0 v cc v input rise or fall times t r , t f v cc =2.0v 1000 ns v cc =4.5v 500 v cc =6.0v 400 operating temperature range t a -40 +85
74hc595 rev 2.2 2013-11-21 5/7 electrical characteristics dc characteristics symbol parameter condition v cc t a =25 t a =25 to 85 t a =-55 to 125 unit typ guaranteed limits v ih minimum high level input voltage 2v 1.5 1.5 1.5 v 4.5v 3.15 3.15 3.15 6v 4.2 4.2 4.2 v il maximum low level input voltage 2v 0.5 0.5 0.5 v 4.5v 1.35 1.35 1.35 6v 1.8 1.8 1.8 v oh minimum high level output voltage v in = v ih or v il i out ? 20 a 2v 2.0 1.9 1.9 1.9 v 4.5v 4.5 4.4 4.4 4.4 6v 6 5.9 5.9 5.9 q h v in = v ih or v il i out ? 4.0ma i out ? 5.2ma 4.5v 4.2 3.98 3.84 3.7 v 6v 5.2 5.48 5.34 5.2 q a to q h v in = v ih or v il i out ? 6.0ma i out ? 7.8ma 4.5v 4.2 3.98 3.84 3.7 v 6.0v 5.7 5.48 5.34 5.2 v ol maximum low level output voltage v in = v ih or v il i out ? 20 a 2v 0 0.1 0.1 0.1 v 4.5v 0 0.1 0.1 0.1 6v 0 0.1 0.1 0.1 q h v in = v ih or v il i out ? 4.0ma i out ? 5.2ma 4.5v 0.2 0.26 0.33 0.4 v 6v 0.2 0.26 0.33 0.4 q a to q h v in = v ih or v il i out ? 6.0ma i out ? 7.8ma 4.5v 0.2 0.26 0.33 0.4 v 6v 0.2 0.26 0.33 0.4 i in maximum input current v in = v cc or gnd 6v f 0.1 f 1.0 f 1.0 a i oz maximum 3-state output leakage v out = v cc or gnd g = v ih 6v f 0.5 f 5.0 f 10 a i cc maximum quiescent supply current v in = v cc or gnd i out = 0 a 6v 8.0 80 160 a
74hc595 rev 2.2 2013-11-21 6/7 ac characteristics (v cc =5v t a =25 t r =t f =6ns) symbol parameter condition typ guaranteed limit unit f max maximum operating frequency of sck 50 30 mhz t phl t plh maximum propagation delay, sck to qh? c l =45pf 12 20 ns t phl t plh maximum propagation delay, rck to qa thru qh c l =45pf 18 30 ns t pzh t pzl maximum output enable time from g to qa thru qh r l =1k ? c l =45pf 17 28 ns t phz t plz maximum output disable time from g to qa to qh r l =1k ? c l =5pf 15 25 ns t s minimum setup time from ser to sck 20 ns t s minimum setup time from sclr to sck 20 ns t s minimum setup time from sck to rck 40 ns t h minimum hold time from ser to sck 0 ns t w minimum pulse width of sck or rck 16 ns ac characteristics (v cc =2. 6.0v c l =50pf t r =t f =6ns) symb ol parameter condition v cc t a =25 t a =25 to 85 t a =-55 to 125 unit typ guaranteed limit f max maximum operating frequency c l =50pf 2v 10 6 4.8 4.0 mhz 4.5v 45 30 24 20 6v 50 35 28 24 t phl t plh maximum propagation delay from sck to qh c l =50pf c l =150pf 2v 58 210 265 315 ns 2v 83 294 367 441 c l =50pf c l =150pf 4.5v 14 42 53 63 ns 4.5v 17 58 74 88 c l =50pf c l =150pf 6v 10 36 45 54 ns 6v 14 50 63 76 t phl t plh maximum propagation delay from rck to qa thru qh c l =50pf c l =150pf 2v 70 175 220 265 ns 2v 105 245 306 368 c l =50pf c l =150pf 4.5v 21 35 44 53 ns 4.5v 28 49 61 74 c l =50pf 6v 18 30 37 45 ns
74hc595 rev 2.2 2013-11-21 7/7 c l =150pf 6v 26 42 53 63 t phl t plh ximum propagation delay from sclr to qh 2v 175 221 261 ns 4.5v 36 44 52 6v 30 37 44 t pzh t pzl maximum output enable from g to qa thru qh r l =1k ? c l =50pf c l =150pf 2v 75 175 220 265 ns 2v 100 245 306 368 c l =50pf c l =150pf 4.5v 15 35 44 53 ns 4.5v 20 49 61 74 c l =50pf c l =150pf 6v 13 30 37 45 ns 6v 17 42 53 63 t phz t plz maximum output disable time from g to qa thru qh r l =1k ? c l =50pf 2v 75 175 220 265 ns 4.5v 15 35 44 53 6v 13 30 37 45 t s minimum setup time from ser to sck 2v 100 125 150 ns 4.5v 20 25 30 6v 17 21 25 t r minimum removal time from sclr to sck 2v 50 63 75 ns 4.5v 10 13 15 6v 9 11 13 t s minimum setup time from sck to rck 2v 100 125 150 ns 4.5v 20 25 30 6v 17 21 26 t h minimum hold time ser to sck 2v 5 5 5 ns 4.5v 5 5 5 6v 5 5 5 t w minimum pulse width of sck or sclr 2v 30 80 100 120 ns 4.5v 9 16 20 24 6v 8 14 18 22 t r t f maximum input rise and fall time, clock 2v 1000 1000 1000 ns 4.5v 500 500 500 6v 400 400 400 t thl t tlh maximum output 2v 25 60 75 90 ns 4.5v 7 12 15 18
74hc595 rev 2.2 2013-11-21 8/7 rise and fall time qa?qh 6v 6 10 13 15 t thl t tlh maximum output rise & fall time qh 2v 75 95 110 ns 4.5v 15 19 22 6v 13 16 19 c pd power dissipation capacitance, outputs enabled g =v cc g =gnd 90 pf 150 c in maximum input capacitance 5 10 10 10 pf c out maximum output capacitance 15 20 20 20 pf
74hc595 rev 2.2 2013-11-21 9/7 package dimension sop16 3.950.10 10.000.10 0.4060.1 1.27 0.200.10 1.450.10 0.203 6.040.20 0.550.20 uni t mm 2 8 tssop16 0.65 4.400.10 6.400.20 4.960.10 1.20max 0.600.15 uni t mm 0.10 0 8 0.90 1.05 0.05 0.15 0.20 0.28 dip16 2.54 7.62 19.100.20 3.800.20 6.350.20 unit mm 3.300.30 0.460.10 1.52 3.300.20 0.254 8.40 9.20 0.75
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